Several Ethernet physical layers defined during recent years use a common physical coding sublayer (PCS) structure defined in clause 82 of the IEEE standard 802.3 (2012). This PCS is modular and enables multiple data rates. In the clause 82 PCS, the incoming data is divided into logical PCS lanes (PCSLs), each carrying 5 Gb/s or 10 Gb/s. Each PCS lane is encoded separately. Data from several PCS lanes may be multiplexed and transmitted over a higher-speed physical communication lane. The clause 82 PCS was designed to support both 40 Gb/s and 100 Gb/s Ethernet, with 100 G implemented as either 10×10 G physical lanes or 4×25 G physical lanes.
Due to possible mismatch between delays in different physical lanes, bits transmitted at the same time over multiple physical lanes may arrive at the receiver in different times. In addition, the Ethernet standard allows re-ordering of physical lanes to allow flexibility in routing. To enable reconstructing the original data sequence, alignment markers (AMs) are inserted in each logical PCS lane periodically. Each AM is a predefined block of data that is different for each lane, so AMs may be used to identify the received lanes and enable de-skewing and re-alignment of the physical lanes. The AMs specified by clause 82 of the Ethernet standard do not support more than 20 logical PCS lanes, and thus may not support scaling to 400 Gb/s Ethernet (e.g., scaling to 40×10 Gb/s PCS lanes or 80×5 Gb/s PCS lanes). Similarly, the forward error correction code defined by clause 91 of the IEEE standard 802.3bj-2014 (RS-FEC) assumes 20 logical PCS lanes and does not support a different number of PCS lanes.